//======================================================================
//    We will gone,the word kept  
//======================================================================
`timescale 1ps/1ps
//=====v1.0====2021.11.10
// tm_axiw.w(pwrite,pwaddr,pwdata)

module tm_axiw
(
	input				sys_rst								,
	input				sys_clk								,
  /**************** Write Address Channel Signals ****************/
  output reg [64-1:0]       			m_axi_awaddr = {64{1'b0}},	//input ,	64bit
  output wire [3-1:0]                     m_axi_awprot	,		//-----fixed,	000
  output reg                             m_axi_awvalid = 1'b0,		
  input  wire                            m_axi_awready,
  output reg [3-1:0]                     m_axi_awsize = 3'b0,		//input，2*size,Burst size. This signal indicates the size of each transfer in the burst
  output reg [2-1:0]                     m_axi_awburst = 2'b0,		//input,just loop the signals;user incr by self;00=fixed;01=INCR;10=WRAP;just support 00/01 
  output wire[4-1:0]                     m_axi_awcache 		,		//-----fixed,=0,Device Non-bufferable
  output reg [8-1:0]				     m_axi_awlen = {8{1'b0}},	//input,just loop the signals,0-255;**0 means 1 transfer
  output wire[1-1:0]       				 m_axi_awlock 			,	//-----fixed,=0
  output wire[4-1:0]                     m_axi_awqos    		,		//-----fixed,=0
  output wire[4-1:0]         			 m_axi_awid  ,	//-----fixed,maybe used ,now =0
  /**************** Write Data Channel Signals ****************/
  output reg [128-1:0]      			 m_axi_wdata,					//input
  output reg [128/8-1:0]     			 m_axi_wstrb = {(128/8){1'b1}}, //input
  output reg                             m_axi_wvalid = 1'b0,
  input  wire                            m_axi_wready,
  output reg                             m_axi_wlast = 1'b0,
  /**************** Write Response Channel Signals ****************/
  input  wire [2-1:0]                    m_axi_bresp,				//error => printf 
  input  wire                            m_axi_bvalid,				// check and be end
  output reg                             m_axi_bready = 1'b0,		
  input  wire [4-1:0]			         m_axi_bid					// no used
  );

//===fixed signal output==
 	assign m_axi_awprot  = 3'b0			;
 	assign m_axi_awcache = 4'b0         ;
 	assign m_axi_awlock  = {1{1'b0}}    ;
 	assign m_axi_awqos   = 4'b0         ;
 	assign m_axi_awid    = {4{1'b0}}    ;
//==task generate signals===	
//bit[63:0] awaddr	;
//bit[128-1:0] wdata	;
//bit[2:0] awsize		;
//bit[1:0] awburst	;
//bit[7:0] awlen		;
//bit[7:0] m_axi_wstrb;
//
reg [7:0]	send_length ;
reg  [7:0]	send_cnt	;
initial begin
			m_axi_awvalid <= 'd0 ;
			m_axi_awaddr  <= 'd0 ;
			m_axi_awsize  <= 'd0 ;
			m_axi_awburst <= 'd0 ;
			m_axi_awlen	  <= 'd0 ;			
			send_cnt	  <= 'd0 ;
			m_axi_bready <= 1'b0 ;
end
 task w(input bit[63:0] awaddr,input bit[128-1:0] wdata,input bit[2:0] awsize,input bit[1:0] awburst,input bit[7:0] awlen, input bit[128/8-1:0] wstrb) ;
		@(posedge sys_clk);
			m_axi_awvalid <= 1'b1;
			m_axi_awaddr  <= awaddr ;
			m_axi_awsize  <= awsize ;
			m_axi_awburst <= awburst;
			m_axi_awlen	  <= awlen  ;
			
			send_cnt	  <= 'd0;
			m_axi_bready <= 1'b0 ;
			while(m_axi_awready==1'b0)  	@(posedge sys_clk)	;//先给地址
			send_length	  <= awlen+1;//2**awsize-1 ;
		@(posedge sys_clk);
			//aw <= 'd0
			m_axi_awvalid <= 'd0;
			m_axi_awaddr  <= 'd0 ;
			m_axi_awsize  <= 'd0 ;
			m_axi_awburst <= 'd0;
			m_axi_awlen	  <= 'd0  ;
			//wdata signals
			m_axi_wdata  = wdata ;//no change,need changed
			m_axi_wstrb	 = {(128/8){1'b1}};//wstrb ;
			m_axi_wvalid = 1'b1  ;
			if (m_axi_wvalid==1'b1 && m_axi_wready==1'b1 && (send_cnt+1==send_length) ) begin
				m_axi_wlast <= 1'b1 ;
				m_axi_wvalid <= 1'b1  ;
				send_cnt	  <= 'd0;;//break;
				m_axi_wstrb	 = wstrb ;
			end else begin
				
				
				while (!(m_axi_wvalid==1'b1 && m_axi_wready==1'b1 && (send_cnt+1==send_length) )) begin
					send_cnt <= (m_axi_wvalid==1'b1 && m_axi_wready==1'b1) ? send_cnt + 1 : send_cnt;
					@(posedge sys_clk) ;
				end
			end
			/*while (m_axi_wready==1'b0) begin
			m_axi_wlast <= 1'b1 ;
			m_axi_wvalid <= 1'b1  ;
			send_cnt	  <= 'd0;
			@(posedge sys_clk);
			end
			*/
			m_axi_wlast <= 1'b1 ;
			m_axi_wvalid <= 1'b1  ;
			send_cnt	  <= 'd0;
			m_axi_wstrb	 = wstrb ;
			@(posedge sys_clk);
			
			m_axi_wlast <= 1'b0 ;
			m_axi_wvalid <= 1'b0  ;
			send_cnt	  <= 'd0;
			m_axi_wstrb	 = {(128/8){1'b1}};//wstrb ;
			//bresp
			m_axi_bready <= 1'b1;	
			while(m_axi_bvalid==1'b1 && m_axi_bready==1'b1) begin
				if 	(m_axi_bresp!=2'b00) $display (" m_axi_bresp != 2'b00") ;

			end
		@(posedge sys_clk);	
			m_axi_bready <= 1'b0;
   endtask
		
           

endmodule


